Field
Embodiments of the present disclosure generally relate to methods of patterning and etching a substrate. More specifically, embodiments described herein relate to material modification and etching processes to manufacture spacer features with a flat top profile.
Description of the Related Art
In response to an increased need for smaller electronic devices with denser circuits, devices with three dimensional (3D) structures, such as fin field effect transistors (FinFETs) have been developed. Forming sub-10 nm node structures is desired but complicated by limitations and complexities associated with various patterning and lithography processes.
For example, multiple patterning processes, such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) processes, may not adequately provide reliable patterning given the small pitch size requirements associated with formation of sub-10 nm node structures. Other lithography processes, such as litho-etch-litho-etch (LELE) processes which utilize 193 nm immersion photolithography, may increase the line width roughness (LWR) of a resist used to pattern features on the substrate.
Conventional double and quadruple double patterning schemes generally involve etching of a spacer material and removal of a mandrel material to leave a mask pattern created by individual spacers. However, conventional spacer etching processes often result in asymmetric spacer profiles. For example, rounding of a spacer shoulder region adjacent a mandrel structure may result in an undesirable pattern transfer during subsequent spacer deposition and etching processes. Inconsistencies and asymmetries in spacer etching may affect pattern transfer which can result in adjacent features having inconsistent critical dimensions, depths, shapes, etc. Moreover, current lithography and patterning processes are time consuming, which reduces throughput for device processing.
Accordingly, improved spacer etching methods are needed.